VLSI

 M.TECH (VLSI)  
CODETITLE
ITnTVL001Design and implementation of truncated multipliers
ITnTVL002Novel High Speed Vedic Mathematics Multiplier using compressors
ITnTVL003Design of High Performance 64 bit MAC Unit
ITnTVL004RADIX 10 PARALLEL Decimal Multiplier
ITnTVL005FPGA Implementation of high speed 8 bit vedic multiplier using barrel shifter.
ITnTVL006An FPGA Based High Speed IEEE-754 Double Precision Floating Point Multiplier
ITnTVL007Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check(EG-LDPC)codes
ITnTVL008Security-Enabled Near-Field Communication Tag With Flexible Architecture Supporting Asymmetric Cryptography
ITnTVL009Techniques for Compensating Memory Errors in JPEG2000
ITnTVL010Low-cost FIR Filter Design Based on Faithfully Rounded Truncated Multiple Constant Multiplication / Accumulation
ITnTVL011MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems
ITnTVL012A Novel Modulo Adder for Residue Number System
ITnTVL013Concurrent error detection for orthogonal Latin squares encoders and syndrome computation
ITnTVL014Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme
ITnTVL015Built in generation of functional broadside tests using a fixed hardware structure
ITnTVL016Achieving Reduced Area By Multi-Bit Flip Flop Design
ITnTVL017Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA
ITnTVL018Design of Digital-Serial FIR Filters: Algorithms, Architecture and a CAD Tool
ITnTVL019Multi operand Redundant Adders on FPGAs
ITnTVL020Computing Two-Pattern Test Cubes for Transition Path Delay Faults
ITnTVL02120-Ghz 8*8 – bit Parallel Carry-Save Pipelined RSFQ Multiplier
ITnTVL022Modulo 2 n -2 Arithmetic Units
ITnTVL023VLSI implementation of Fast Addition using Quaternary Signed Digit Number System
ITnTVL024A Novel VLSI DHT algorithm for highly modular and parallel architecture
ITnTVL025A low power single phase clock distribution using VLSI technology
ITnTVL026Area efficient parallel FIR digital filter structure for symmetric convolutions based on fast FIR algorithm
ITnTVL027A novel approach for parallel CRC generation for high speed applications
ITnTVL028Design and Implementation of High-Performance High-Valency Ling Adders
ITnTVL029An On-Chip Delay Measurement Technique Using Signature Registers For Small-Delay Defect Detection
ITnTVL030Period Extension And Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG
ITnTVL031Single Cycle Access Structure For Logic Test
ITnTVL032A Low-Power Single-Phase Clock Multiband Flexible Divider
ITnTVL033ON MODULO 2 n + 1 ADDER DESIGN
ITnTVL034Low-Power and Area-Efficient Carry Select Adder
ITnTVL035Accumulator Based 3-Weight Pattern Generation
ITnTVL036Platform-Independent Customizable UART Soft-Core
ITnTVL037An efficient FPGA implementation of the Advanced Encryption Standard algorithm
ITnTVL038Implementation of a Flexible and Synthesizable FFT Processor
ITnTVL039Reliable and Cost Effective Anti-coll ision Technique for RFID UHF Tag
ITnTVL040Self-Immunity Technique to Improve Register File Integrity against Soft Errors
ITnTVL041Radix-8 Booth Encoded Modulo 2n-1 Multipliers With Adaptive Delay For High Dynamic Range Residue Number System
ITnTVL042A Spurious-Power Suppression Technique for Multimedia/DSP Applications (MAC)
ITnTVL043Reducing the Computation Time in (Short Bit-Width) Twos Complement Multipliers
ITnTVL044Multi-operand Redundant Adders on FPGAs
ITnTVL045Scalable Digital CMOS Comparator Using a Parallel Prefix Tree
ITnTVL04616-Bit Wave-Pipelined Sparse-Tree RSFQ Adder
ITnTVL047The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures
ITnTVL048MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems
ITnTVL049Efficient RNS Implementation of Elliptic Curve Point Multiplication Over GF(p)
ITnTVL050Pipelined Radix- Feedforward FFT Architectures
ITnTVL051Error Detection in Majority Logic Decoding of euclidean Geometry Low Density Parity Check (EG-LDPC) Codes
ITnTVL052Design of Testable Reversible Sequential Circuits
ITnTVL053Design of Digit-Serial FIR Filters: Algorithms
ITnTVL054Architecture for Real-Time Nonparametric Probability Density Function Estimation
ITnTVL055Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme
ITnTVL056Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay
ITnTVL057Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code
ITnTVL058High-Throughput Multi standard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic
ITnTVL059Comments on “Low-Energy CSMT Carry Generators and Binary Adders
ITnTVL060FFT Architectures for Real-Valued Signals Based on Radix- and Radix- Algorithms
ITnTVL061FPGA Architecture for OFDM Software Defined Radio with an optimized Direct Digital Frequency Synthesizer
ITnTVL062Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/Accumulation
ITnTVL063A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories
ITnTVL064An Energy-Efficient L2 Cache Architecture Using Way Tag
ITnTVL065Low-Complexity Multiplier for GF(2^m) Based on All-One Polynomials
ITnTVL066CORDIC Designs for Fixed Angle of Rotation
ITnTVL067Pipelined Parallel FFT Architectures via Folding Transformation
ITnTVL068A Novel Modulo Adder for 2^n-2^k-1 Residue Number System
ITnTVL069UnSync-CMP: Multi-core CMP Architecture for Energy Efficient Soft Error Reliability
ITnTVL070HaDeS: Architectural Synthesis for Heterogeneous Dark Silicon Chip Multi-processors
ITnTVL071FaulTM: Error Detection and Recovery Using Hardware Transactional Memory
ITnTVL072SMART: A Single-Cycle Reconfigurable NoC for SoC Applications
ITnTVL073Mixed-Signal System-on-a-Chip (SoC) Verification Based on SystemVerilog Model
ITnTVL074C-Lock : Energy Efficient Synchronization for Embedded Multicore Systems
ITnTVL075Low-Latency Maximal-Throughput Communication Interfaces for Rationally Related Clock Domains
ITnTVL076Designing a Physical Locality Aware Coherence Protocol for Chip-Multiprocessors
ITnTVL077Cache Coherence for GPU Architectures
ITnTVL078Importance of Coherence Protocols with Network Applications on Multicore Processors
ITnTVL079Efficient Register Renaming and Recovery for High-Performance Processors
ITnTVL080Scalability Analysis of Memory Consistency Models in NoC-based Distributed Shared Memory SoCs
ITnTVL081On-the-Field Test and Configuration Infrastructure for 2-D-Mesh NoCs in Shared-Memory Many-Core Architectures
ITnTVL082The Next Generation 64b SPARC Core in a T4 SoC Processor
ITnTVL083A Multi-Agent Framework for Thermal Aware Task Migration in Many-Core Systems
ITnTVL084A High-Precision On-Chip Path Delay Measurement Architecture
ITnTVL085Full Fault Resilience and Relaxed Synchronization Requirements at the Cache-Memory Interface
ITnTVL086Building an AMBA AHB compliant Memory Controller
ITnTVL087Hardware Synchronization for Embedded Multi-Core Processors
ITnTVL088Location Cache Design and Performance Analysis for Chip Multiprocessors
ITnTVL089On chip Implementation of Advanced Microcontroller Bus Architecture (AMBA).
NETWORK ON CHIP DESIGNS ( NoCs)
ITnTNO001Traffic- and Thermal-aware Adaptive Beltway Routing for Three Dimensional Network-on-Chip Systems
ITnTNO002Implementation of ACO-based Selection with Backward-Ant Mechanism for Adaptive Routing in Network-on-Chip Systems
ITnTNO003Enhanced Fault-Tolerant Network-on-Chip Architecture Using Hierarchical Agents
ITnTNO004ROUTE-O-MATIC: A Comprehensive Framework for Reactive Mesh Routing Protocols
ITnTNO005FPGA Based Single Cycle, Reconfigurable Router for NoC Applications
ITnTNO006Smart Reliable Network-on-Chip
ITnTNO007EnergyEfficient Interconnect via Router Parking
ITnTNO008UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors
ITnTNO009FL2STAR: A Novel Topology For On-Chip Routing in NoC with Fault Tolerance and Deadlock Prevention
ITnTNO010SMART: A Single-Cycle Reconfigurable NoC for SoC Applications
ITnTNO011A Reliable Routing Architecture and Algorithm for NoCs
ITnTNO012On Self-tuning Networks-on-Chip for Dynamic Network-Flow Dominance Adaptation
ITnTNO013Randomized Throughput-Optimal Oblivious Routing for Torus Networks
ITnTNO014Enhancing Performance of 3D Interconnection Networks Using Efficient Multicast Communication Protocol
ITnTNO015Achieving High-Performance On-Chip Networks With Shared-Buffer Routers
ITnTNO016Low-Latency Maximal-Throughput Communication Interfaces for Rationally Related Clock Domains
ITnTNO017Ultra-High Throughput Low-Power Packet Classification
ITnTNO018Mass Message Transmission Aware Buffer-Less Packet-Circuit Switching Router for 3D NoC
ITnTNO019Fault-Tolerant Routing Algorithm for 3D NoC Using Hamiltonian Path Strategy
ITnTNO020Headfirst Sliding Routing: A Time-Based Routing Scheme for Bus-NoC Hybrid 3-D Architecture
ITnTNO021Fault-tolerant Network Interfaces for Networks-on-Chip
ITnTNO022Routing-Based Traffic Migration and Buffer Allocation Schemes for 3-D Network-on-Chip Systems With Thermal Limit
ITnTNO023Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip
ITnTNO024Ultra-High Throughput Low-Power Packet Classification
ITnTNO025CusNoC: Fast Full-Chip Custom NoC Generation
ITnTNO026An Analytical Latency Model for Networks-on-Chip
ITnTNO027SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects
ITnTNO028Combined Architecture/Algorithm Approach to Fast FPGA Routing
ITnTNO029Networks-in-Cache for High- Performance Low-Power Embedded Processors
ITnTNO030Randomized Partially-Minimal Routing: Near-Optimal Oblivious Routing for 3-D Mesh Networks
ITnTNO031Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router
ITnTNO032Semi-Serial On-Chip Link Implementation for Energy Efficiency and High Throughput
ITnTNO033Dual-Layer Adaptive Error Control for Network-on-Chip Links
ITnTNO034Design and Implementation of Backtracking Wave-Pipeline Switch to Support Guaranteed Throughput in Network-on-Chip
ITnTNO035Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph
ITnTNO036A Variation Tolerant Current-Mode Signaling Scheme for On-Chip Interconnects
ITnTNO037Reconfigurable Routers for Low Power and High Performance
ITnTNO038A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors
ITnTNO039Design and FPGA Implementation of feed forward Neural Network
ITnTNO040A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors
PROCESSOR DESIGN
ITnTPD001A Reconfigurable Application-specific Instruction-set Processor for Fast Fourier Transform Processing
ITnTPD002A Run-Time Adaptive Multiprocessor System
ITnTPD003Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications
ITnTPD004Secure Dual-Core Cryptoprocessor for Pairings Over Barreto-Naehrig Curves on FPGA Platform
ITnTPD005Portable, Flexible, and Scalable Soft Vector Processors
ITnTPD006A Reconfigurable Gf(^m) Elliptic Curve Cryptographic(ECC) Co Processor
ITnTPD00716-Bit RISC processor design for convolution application
ITnTPD008A High-Performance Unified-Field Reconfigurable Cryptographic Processor
CORE VLSI
ITnTCV001A Low-Power Single-Phase Clock Multiband Flexible Divider
ITnTCV002Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops
ITnTCV003A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor
ITnTCV004All-Digital Wide Range Precharge Logic % Duty Cycle Corrector
ITnTCV005C-Based Complex Event Processing on Reconfigurable Hardware
ITnTCV006The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures
ITnTCV007A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs
ITnTCV008A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time
ITnTCV009A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic
SECURITY ALGORITHMS
ITnTSA001Efficient RNS Implementation of Elliptic Curve Point Multiplication Over GF(p)
ITnTSA002Exploiting Vulnerabilities in Cryptographic Hash Functions Based on Reconfigurable Hardware
ITnTSA003High-Performance Implementation of Point Multiplication on Koblitz Curves
ITnTSA004SecureCore: A Multicore-based Intrusion Detection Architecture for Real-Time Embedded Systems
ITnTSA005Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture
ITnTSA006Exploiting Vulnerabilities in Cryptographic Hash Functions Based on Reconfigurable Hardware
ITnTSA007A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores
ITnTSA008Secure Dual-Core Cryptoprocessor for Pairings Over Barreto-Naehrig Curves on FPGA Platform
ITnTSA009Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis
ITnTSA010FPGA Implementation of Humming bird cryptographic algorithm
ITnTSA011Design and Implementation of Area-optimized AES Based on FPGA
ITnTSA012Fast Elliptic Curve Cryptography (ECC)on FPGA
ITnTSA013Single Chip Encryptor Decryptor Core Implementation of AES Algorithm
Digital CMOS Designs / HSPICE Simulation Topics
ITnTDCHS001Average-8T Differential-Sensing Subthreshold SRAM With Bit Interleaving and 1k Bits Per Bitline
ITnTDCHS002A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop
ITnTDCHS003Current-Comparison-Based Domino: New Low-Leakage High-Speed Domino Circuit for Wide Fan-In Gates
ITnTDCHS004Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme
ITnTDCHS005Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design
ITnTDCHS006Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops
ITnTDCHS007Enhancing NBTI Recovery in SRAM Arrays Through Recovery Boosting
ITnTDCHS008Postsilicon Tuning of Standby Supply Voltage in SRAMs to Reduce Yield Losses Due to Parametric Data-Retention Failures
ITnTDCHS009A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor
ITnTDCHS010Self-Repairing SRAM Using On-Chip Detection and Compensation
ITnTDCHS011A Discussion on SRAM Circuit Design Trend in Deeper Nanometer-Scale Technologies (8T,10T,11T ,12T based SRAM designs )
MEMORIES
ITnTM001Area Efficient ROM-Embedded SRAM Cache
ITnTM002FPGA-RPI: A Novel FPGA Architecture With RRAM-Based Programmable Interconnects
ITnTM003AWARE (Asymmetric Write Architecture with REdundant blocks): A High Write Speed STT-MRAM Cache Architecture
ITnTM004Large-Scale Memristive Associative Memories
ITnTM005Exploiting Early Tag Access for Reducing L1 Data Cache Energy in Embedded Processors
ITnTM006An Event-Based Neural Network Architecture With an Asynchronous Programmable Synaptic Memory
ITnTM007Temperature Sensing RRAM Architecture for 3-D ICs
ITnTM008Partial Parity Cache and Data Cache Management Method to Improve the Performance of an SSD-Based RAID
ITnTM009STT-RAM Cache Hierarchy With Multiretention MTJ Designs
ITnTM010STT-MRAM Sensing CircuitWith Self-Body Biasing in Deep Submicron Technologies
ITnTM011Exploiting Early Tag Access for Reducing L1 Data Cache Energy in Embedded Processors
ITnTM012Nonvolatile CBRAM-Crossbar-Based 3-D-Integrated Hybrid Memory for Data Retention
ITnTM013Using Magnetic RAM to Build Low-Power and Soft Error-Resilient L1 Cache
ITnTM014Run-Time Reconfiguration of Expandable Cache for Embedded Systems
ITnTM015SRAM-Based NATURE: A Dynamically Reconfigurable FPGA Based on 10T Low-Power SRAMs
ITnTM016Efficient Memory Repair Using Cache-Based Redundancy
ITnTM017An Energy-Efficient L2 Cache Architecture Using Way Tag Information Under Write-Through Policy
ITnTM018Exploring the Use of Emerging Nonvolatile Memory Technologies in Future FPGAs
ITnTM019Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications
ITnTM020Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling
ITnTM021Enhancing NBTI Recovery in SRAM Arrays Through Recovery Boosting
ITnTM022Design of a NoC Interface Macrocell with Hardware Support of Advanced Networking Functionalities
ITnTM023C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
ITnTM024Reconfigurable Cache implemented on an FPGA
VLSI TOPICS ON WIRELESS / COMMUNICATIONS
ITnTVC001A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks
ITnTVC002Reconfigurable FFT using CORDIC based architecture for MIMO-OFDM receivers
ITnTVC003Efficient Shuffled Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes
ITnTVC004Energy Efficient Programmable MIMO Decoder Accelerator Chip in 65-nm CMOS
ITnTVC005Nonbinary LDPC Decoder Based on Simplified Enhanced Generalized Bit-Flipping Algorithm
ITnTVC006Synthesis and Array Processor Realization of a 2-D IIR Beam Filter for Wireless Applications
ITnTVC007High-Speed Low-Power Viterbi Decoder Design for TCM Decoders
ITnTVC008Unified Architecture for Reed-Solomon Decoder Combined With Burst-Error Correction
ITnTVC009Novel MIMO Detection Algorithm for High-Order Constellations in the Complex Domain
ITnTVC010Trellis-Search Based Soft-Input Soft-Output MIMO Detector: Algorithm and VLSI Architecture
ITnTVC011A Scalable SDH/SONET Framer Architecture On VLSI Technology
ITnTVC012Precision-Aware Self-Quantizing Hardware Architectures for the Discrete Wavelet Transform
ITnTVC013High-Throughput, Lossless Data Compression on FPGAs
ITnTVC014An Energy-Efficient Partial FFT Processor for the OFDMA ommunication System
ITnTVC015VLSI Implementation of a High-Throughput Soft-Bit-Flipping Decoder for Geometric LDPC Codes
ITnTVC016A Multibank Memory-Based VLSI Architecture of DVB
ITnTVC017Design of a Novel FSM Based Reconfigurable Multimode Interleaver for WLAN Application
ITnTVC018VLSI Design of an OFDM Transmission scheme ( Verilog design of OFDM Tx , Rx )
VLSI TOPICS ON DIGITAL SIGNAL PROCESSING ( DSP ) DESIGNS
ITnTVCD001Reconfigurable FIR Filter Using Distributed Arithmetic on FPGAs
ITnTVCD002A Memory-Efficient Scalable Architecture for Lifting-Based Discrete Wavelet Transform
ITnTVCD003Jointly Designed Architecture-Aware LDPC Convolutional Codes and Memory-Based Shuffled Decoder Architecture
ITnTVCD004An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform
ITnTVCD005Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection
ITnTVCD006CORDIC Designs for Fixed Angle of Rotation
ITnTVCD007Synthesis and Array Processor Realization of a 2-D IIR Beam Filter for Wireless Applications
ITnTVCD008VLSI Architecture of Arithmetic Coder Used in SPIHT
ITnTVCD009Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm
ITnTVCD010Precision-Aware Self-Quantizing Hardware Architectures for the Discrete Wavelet Transform
ITnTVCD011Blind source separation based on DUET algorithgm using DFT
ITnTVCD012A Low-Cost VLSI Implementation for Efficient Removal of Impulse Noise in images_Sim
ITnTVCD013Novel Area-Efficient FPGA Architectures for FIR Filtering With Symmetric Signal Extension
DESIGN FOR TEST( DFT )
ITnTVDFT001Low-Cost Scan-Chain-Based Technique to Recover Multiple Errors in TMR Systems
ITnTVDFT002Test Strategies for Reliable Runtime Reconfigurable Architectures
ITnTVDFT003MIHST: a Hardware Technique for Embedded Microprocessor Functional On-line Self-Test
ITnTVDFT004MIHST: a Hardware Technique for Embedded Microprocessor Functional On-line Self-Test
ITnTVDFT005Low-Cost Self-Test Techniques for Small RAMs in SOCs Using Enhanced IEEE 1500 Test Wrappers
ITnTVDFT006Soft-Error-Resilient FPGAs Using Built-In -D Hamming Product Code
ITnTVDFT007Physical-Defect Modeling and Optimization for Fault-Insertion Test
ITnTVDFT008Formal Performance Analysis for Faulty MIMO Hardware
ITnTVDFT009Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure
ITnTVDFT010A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores
ITnTVDFT011An Area Effective Parity-Based Fault Detection Technique for FPGAs
ITnTVDFT012Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis
ITnTVDFT013Built-In Self-Test of Embedded SEU Detection Cores in Virtex- and Virtex- FPGAs
ITnTVDFT014Fault Tolerance of SRAM-based FPGA Via Configuration Frames
ITnTVDFT015Injecting Intermittent Faults for the Dependability Validation of Commercial Microcontrollers
OTHERS
ITnTO001Reconfigurable Accelerator for the Word-Matching Stage of BLASTN
ITnTO002Parallel FPGA-based Implementation of Recursive Sorting Algorithms
ITnTO003Efficient Pattern Matching Algorithm for Memory Architecture
ITnTO004FPGA Designs with Optimized Logarithmic Arithmetic ( LNS ) using DCT